1. Field of the Invention
The present invention generally relates to a sampling method and a data recovery circuit using the same, in particular, to a sampling method offering improved accuracy in data sampling and a data recovery circuit using the same.
2. Description of Related Art
In a high-speed serial link system, mismatch of semiconductor processes or chip layouts, differences in wire-interconnect lengths, temperature variations, variations in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock and signal channels always results in asynchrony or skew between strobes and data received by a receiver.
FIG. 1 is a timing diagram of a strobe and a data received by a receiver. As shown in FIG. 1, when the strobe CLK1 received by the receiver is synchronous to the strobe CLK2 of the phase locked loop (PLL), the digital signal DATA received by the receiver is then sampled at the falling edges of the strobe CLK2. Ideally, the data transition points of the digital signal DATA should align with the rising edges of the strobe CLK2. Accordingly, data sampling is carried out at the middle point (i.e. the optimal data sampling point 102 in FIG. 1) of each bit of the digital signal DATA in order to obtain correct data.
However, skews may be caused when the digital signal DATA lags or leads the strobe CLK2. FIG. 2 is another timing diagram of a strobe and a data received by a receiver. Skew 202 is caused when the data transition points of the digital signal DATA are not aligned with the rising edges of the strobe CLK2. If the skew 202 is too large, the falling edges of the strobe CLK2 fall exactly around the data transition points of the digital signal DATA (as denoted by symbol 204). In this case, incorrect data may be obtained.
To resolve foregoing problem, an over sampling technique is disclosed in U.S. Pat. No. 5,905,769. FIG. 3 is a timing diagram of a sampling strobe and a digital signal according to the conventional over sampling technique. In FIG. 3, symbols 24-1˜24-12 represent the rising edges or the falling edges of the sampling strobe, which can be referred as sampling edges. Symbols 28-1˜28-4 represent four bits in the digital signal DATA, and the values of bits 28-1˜28-4 are respectively 1, 0, 1, and 0. Symbols S[0]˜S[11] represent the sampling results at different time points, and the number above each sampling result represents the sampled value. As shown in FIG. 3, the frequency of sampling is increased therefore each bit is sampled three times. Taking the first three sampling results S[0]˜S[2] as example, it can be determined that the value of the first bit (i.e. bit 28-1) is 1 because all the sampled values of the three sampling results are 1.
Through the over sampling technique described above, correct data can be obtained when the digital signal and the sampling strobe are asynchronous. FIG. 4 is yet another timing diagram of a sampling strobe and a digital signal according to the conventional over sampling technique. Referring to FIG. 4, still taking the first three sampling results S[0]˜S[2] as example, it can also be determined that the value of the first bit (i.e. bit 28-1) is 1 because two of the sampled values of the three sampling results are 1 and only one of them is 0. In other words, as long as two of the three sampled values are the same, this value is used as the value of the sampled bit.
However, even though foregoing over sampling technique can increase the accuracy of data sampling, the values of sampled bits may be determined incorrectly when the skews between the digital signal and the sampling strobe are very large and accordingly the sampling edges of the sampling strobe fall on the data transition points of the digital signal.